The present invention refers in general to CMOS Silicon-On-Insulator (SOI) technology and, more specifically, to an SOI FET having a body contact. It is also concerned with a method of forming such a transistor.
Silicon-on-Insulator (SOI) technology is becoming extremely attractive for future high performance low power applications. Partially depleted SOI technology offers a variety of practical advantages such as ease of manufacturing, better control of threshold voltage and tighter control of short channel effects than fully depleted devices.
In the traditional CMOS bulk process (cf. FIGS. 1A to 1C) a transistor is formed by a poly-silicon gate 1 (extending along a gate axis) and the source/drain diffusion region 2 to the left and right of the gate. The region 3 under the gate is the active area of the device, p-type for a n-FET device, n-type for a p-FET.
In the following an n-FET is taken to describe the device characteristics but they are also applicable to a p-FET with inverted polarities and conductivity types.
The region under the gate is also called the body 3 of the device. Source and drain are n-type diffusions and are separated by the p-type body. A positive voltage on the gate converts the p-type silicon thereunder to n-type and forms a thin channel between source and drain, thus a current can flow between source and drain.
Adjacent devices are separated by a trench oxide 4 (STIxe2x80x94silicon trench isolation) to increase density and prevent latch-up effects (parasitic bipolar current).
The performance of a CMOS circuit mainly depends on the maximum current of the device and the total capacitance it has to charge. The current is a complex function of many technology characteristics but as a first approximation the channel length and the threshold voltage Vt are the key parameters. The channel length is defined as the distance between source and drain, the current increases with a smaller channel length. The threshold voltage is the voltage needed on the gate to build the channel. While the channel length is of a physical nature, Vt is a function of many independent physical parameters like gate oxide thickness, doping concentrations and electrical conditions like the body voltage. A positive body voltage lowers the threshold so that the device can switch earlier and the maximum current is increased. The device is faster but also has a higher leakage. To guarantee a reliable function and prevent parasitic bipolar currents between devices through npnp structures (latch-up effect) the body of the device is usually tied to ground through the backside of the silicon wafer or by adjacent body contacts.
Wiring and device capacitance contribute to the total capacitance a device has to drive. The device caps are mainly the gate-to-body cap (Cg), the gate-to-source/drain overlap caps (Cgs, Cgd) and the source/drain diffusion caps (Cs, Cd).
In contrast to the bulk technology, the SOI technology employs a layer of silicon overlying an insulating material (usually silicon oxide) on a supporting bulk wafer.
Thus, the active area now is in the top silicon layer (device layer) on top of the buried oxide. The device layer thickness is smaller than the depth of the STI oxide so that the two isolations touch each other. This results in totally isolated devices, there is no longer any connection to the body through the backside of the wafer. The STI acts as a wall surrounding the devices, the buried oxide is the isolating floor.
The body of each device is floating. During current flow through the device impact ionization into the body charges up the body. The voltage level depends on the history of the device, i.e., how often it has switched and the total capacitance it had to drive. The minimum is usually ground for an n-type device, the maximum is limited by the forward diode behavior of the source/drain diffusion and is in the order of a few hundred millivolts. As already mentioned with respect to the bulk technology the threshold voltage and the maximum current of a device are a function of the body voltage. In average the body has a positive potential which lets the device switch earlier because of the lower Vt, the current reaches the maximum value faster and the maximum is higher. While a current flows through the device, more charge leaks into the body. Because of impact ionization at the drain diode of the device, the potential increases and, in turn, also the current (kink effect). As a rough estimation all of these effects result in about (10+xc3x97) % performance improvement.
Negative effects are the increased leakage currents due to the reduced Vt and a bipolar n-p-n structure (source-body-drain) which can be electrically activated by a positive bias on the base of the parasitic bipolar npn transistor, (i.e., body potential) and results in additional leakage.
Because the body potential now is a function of the device history, the behavior changes over time, there is no longer a fixed delay for a specific circuit, it is only possible to assign a min/max value to each circuit. This, however, causes many problems: analog circuits are hard to control, dynamic logic has to fight with race conditions and increased leakage, the min/max delay characteristics have to be determined, chip integration has to respect a worst case scenario for min/max delay combinations on all the logical units, etc. In some situations where exact timing is important (race conditions in dynamic logic) or symmetrical devices are needed (sense amplifier in cache arrays) a body contact on the transistor gives control over the body potential.
SOI also affects the device capacitance. The source/drain diffusions touch the buried oxide which eliminates the source/drain diffusion capacitance, it nearly goes down to zero. In cases where a circuit has to drive a long wire, the total capacitance is mainly the wiring capacitance (which is the same as that of the bulk process). The diffusion contribution is very small and in total there is nearly no change. But in case of dotted-or situations (like multiplexers or bit lines in arrays) the diffusion has a significant contribution to the total capacitance. As a rule of thumb one can expect an improvement of up to 10% in average due to the elimination of the diffusion capacitance.
In total this results in a 20% performance advantage of SOI over bulk technology.
The body of an SOI device is totally isolated by the buried oxide and the shallow trench isolation. In a normal n-FET device there is no direct access to the body because the source/drain diffusions are n-type while the body is p-type. In order to get access to the body an additional p-type region must be provided which can be contacted from the surface.
Several proposals have been made in the art concerning the provision of SOI transistors including body contacts. In U.S. Pat. No. 5,489,792, Hu et al. propose an SOI MOSFET having improved electrical characteristics, this MOSFET including a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization.
Bronner et al., in U.S. Pat. No. 5,606,188, propose an SOI DRAM including a direct body contact between the SOI layer and the silicon substrate, and field-shield isolation positioned on the surface of the SOI structure which extends over the direct body contact.
In U.S. Pat. No. 5,729,039 to Beyer et al., there is disclosed an SOI transistor having a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body.
As already mentioned before, dynamic floating body effects have generated considerable problems. Controlling the body voltage has become an issue in situations where a mismatch in threshold voltages between devices (e.g., SRAM sense-amplifiers) or history dependent delays are not acceptable.
An SOI MOS transistor is disclosed in U.S. Pat. No. 5,185,280 to Houston et al., that has an implanted region of the same conductivity type as the body underneath one or both of the extended drain and source portions of the drain and the source with and without a body-to-source (BTS) contact or a general body contact. The floating body effects are said to be minimized by this arrangement. One embodiment is a method of controlling the body voltage by contacting it from the edge of the transistor. The body is elongated at the edge of the transistor and a contact is made to the body. Thus, a polysilicon T-shape acts as the insulation between the p-region and the n-source/drain region.
However, just because of this T-shape, the gate capacitance is increased by about 20% (and more for smaller devices), because it represents an additional area which is parasitic and thus increases the capacitance and leads to a slowdown of the transistor, resulting in a performance reduction of about the same order of 20%.
As an example, Table 1 shows the gate capacitance and delay of a 18/9 xcexcm CMOS inverter (body floating), wherein RF represents the delay rising input to falling output and FR represents the delay falling input to rising output.
fF=femto Farad; ps=pico seconds
It is therefore an object of the present invention to provide a body contact for an SOI CMOS device without any increase in capacitance and delay.
It is a further object to provide such a body contact that is self-aligning with respect to the width of the device.
It is still another object of the present invention to provide a method of making such a body contact that does not require additional process steps.
Due to the fact that the T-shape has to overlap the diffusion region for process tolerance reasons, a minimum distance from the rail of the T-shape to the adjacent geometries is required (polysilicon to polysilicon and polysilicon to diffusion). Using the present invention eliminates the rail and its overlap and thus results in a higher density. Furthermore, it allows an easy migration of designs in the traditional bulk process to SOI because the device area is not enlarged by the T-shape and the design effort to adjust the layout is minimized.